Khurshid, Burhan: search on Z-Library

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1

Achieving environmental sustainability through information technology: “Digital Pakistan” initiative for green development

Nizam, Hassan Ahmad, Zaman, Khalid, Khan, Khan Burhan, Batool, Rubeena, Khurshid, Muhammad Adnan, Shoukry, Alaa Mohamd, Sharkawy, Mohamed A., Aldeek, Fares, Khader, Jameel, Gani, Showkat

Journal:

Environmental Science and Pollution Research

Year:

2020

Language:

english

File:

PDF, 464 KB

english, 2020

2

[IEEE 2019 6th International Conference on Signal Processing and Integrated Networks (SPIN) - Noida, India (2019.3.7-2019.3.8)] 2019 6th International Conference on Signal Processing and Integrated Networks (SPIN) - Performance Evaluation of Fixed-Point Array Multipliers on Xilinx FPGAs

Khurshid, Burhan, Syed, Saniya, Mehtaab, Syed, Peerzada, Junaid, Yaqoob, Adnan

Year:

2019

Language:

english

File:

PDF, 2.97 MB

english, 2019

3

[IEEE 2019 6th International Conference on Signal Processing and Integrated Networks (SPIN) - Noida, India (2019.3.7-2019.3.8)] 2019 6th International Conference on Signal Processing and Integrated Networks (SPIN) - Achieving Performance Speed-Up in FPGA Based FIR Filters Using DSP Macro Blocks

Khurshid, Burhan, Manzoor, Mayidah, Muzaffar, Kurteeba, Wani, Bazilla, Mushtaq, Basit

Year:

2019

Language:

english

File:

PDF, 276 KB

english, 2019

4

Efficient Realization of Fixed-Point Binary and Ternary Adders on FPGAs

Khurshid, Burhan, Naaz, Roohie

Journal:

Journal of Circuits System and Computers

Year:

2016

Language:

english

File:

PDF, 963 KB

english, 2016

5

Technology-Optimized Fixed-Point Bit-Parallel Multipliers for FPGAs

Khurshid, Burhan

Journal:

Journal of Signal Processing Systems

Year:

2016

Language:

english

File:

PDF, 6.00 MB

english, 2016

6

Improved Synthesis of Generalized Parallel Counters on FPGAs Using Only LUTs

Khurshid, Burhan

Journal:

Journal of Circuits System and Computers

Year:

2017

Language:

english

File:

PDF, 2.11 MB

english, 2017

7

[IEEE 2015 2nd International Conference on Electronics and Communication Systems (ICECS) - Coimbatore, India (2015.2.26-2015.2.27)] 2015 2nd International Conference on Electronics and Communication Systems (ICECS) - Technology optimized fixed-point bit-parallel multiplier for LUT based FPGAs

Khurshid, Burhan, Nazir, Liyaqat, Mir, Roohie Naaz

Year:

2015

Language:

english

File:

PDF, 246 KB

english, 2015

8

High Efficiency Generalized Parallel Counters for Look-Up Table Based FPGAs

Khurshid, Burhan, Mir, Roohie Naaz

Journal:

International Journal of Reconfigurable Computing

Year:

2015

Language:

english

File:

PDF, 2.35 MB

english, 2015

9

Technology optimised fixed-point bit-parallel multiplier for LUT-based FPGAs

Khurshid, Burhan, Naaz, Roohie

Journal:

International Journal of High Performance Systems Architecture

Year:

2016

Language:

english

File:

PDF, 253 KB

english, 2016

10

LUT based realization of fixed-point multipliers targeting state-of-art FPGAs

Khurshid, Burhan

Journal:

Design Automation for Embedded Systems

Year:

2017

Language:

english

File:

PDF, 1.38 MB

english, 2017

11

[IEEE 2014 27th International Conference on VLSI Design - India (2014.01.5-2014.01.9)] 2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems - A Hardware Intensive Approach for Efficient Implementation of Numerical Integration for FPGA Platforms

Khurshid, Burhan, Mir, Roohie Naz

Year:

2014

Language:

english

File:

PDF, 291 KB

english, 2014

12

An Efficient Fixed-Point Multiplier based on CORDIC Algorithm

Khurshid, Burhan, Khan, Javeed Jeelani

Journal:

Journal of Circuits System and Computers

Year:

2020

File:

PDF, 1.08 MB

2020

13

[IEEE 2015 International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI-SATA) - Bengaluru, India (2015.1.8-2015.1.10)] 2015 International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI-SATA) - Power efficient implementation of bit-parallel unrolled CORDIC structures for FPGA platforms

Khurshid, Burhan, Mir, Roohie Naaz

Year:

2015

Language:

english

File:

PDF, 1.16 MB

english, 2015

14

An Efficient FIR Filter Structure Based on Technology-Optimized Multiply-Adder Unit Targeting LUT-Based FPGAs

Khurshid, Burhan, Mir, Roohie Naaz

Journal:

Circuits, Systems, and Signal Processing

Year:

2017

Language:

english

File:

PDF, 2.88 MB

english, 2017

15

[IEEE 2014 International Conference on Signal Processing and Integrated Networks (SPIN) - Noida, Delhi-NCR, India (2014.02.20-2014.02.21)] 2014 International Conference on Signal Processing and Integrated Networks (SPIN) - A hybrid-radix approach for efficient implementation of unfolded CORDIC architectures for FPGA platforms

Khurshid, Burhan, Mir, Roohie Naz, Kumar, Animesh, Kumar, Shatish

Year:

2014

Language:

english

File:

PDF, 277 KB

english, 2014

16

[IEEE 2015 IEEE 22nd International Conference on High Performance Computing (HiPC) - Bengaluru, India (2015.12.16-2015.12.19)] 2015 IEEE 22nd International Conference on High Performance Computing (HiPC) - High Efficiency Generalized Parallel Counters for Xilinx FPGAs

Khurshid, Burhan, Mir, Roohie Naaz

Year:

2015

Language:

english

File:

PDF, 197 KB

english, 2015

17

[IEEE 2015 Annual IEEE India Conference (INDICON) - New Delhi, India (2015.12.17-2015.12.20)] 2015 Annual IEEE India Conference (INDICON) - Improving synthesis of fixed-point adders on FPGAs using primitive instantiations

Khurshid, Burhan, Naaz, Roohie

Year:

2015

Language:

english

File:

PDF, 665 KB

english, 2015

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